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hardware:dbbc3 [2019/02/19 02:49] Guifre |
hardware:dbbc3 [2019/03/11 23:49] Guifre |
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* VNC connection with standard pwd | * VNC connection with standard pwd | ||
* remote desktop with Windows XP user/pwd | * remote desktop with Windows XP user/pwd | ||
+ | === Installation DDC_V_v123 | ||
+ | Notes provided in 20.11.2018 | ||
+ | |||
+ | - Copy **executable** file 'DBBC3 Control_V_v123.exe' into bin folder or Desktop | ||
+ | - Copy **firmware** files 'dbbc3_ddc-V_v123*.bit' into DBBC_CONF/FilesDBBC | ||
+ | - Copy **config** files: | ||
+ | * 'dbbc3_config_file_V_123.txt' | ||
+ | * 'config_ddc_V.txt' / 'config_ddc_V_12bbc.txt' | ||
+ | * 'config_adb3l.txt' | ||
+ | * 'ddc_v_core3H_#.fila10g' / ddc_V_12bbc_core3H_#.fila10g' | ||
==== Start DBBC3 Control ==== | ==== Start DBBC3 Control ==== | ||
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- Calibrate gain | - Calibrate gain | ||
- | ===== Calibrate offset ===== | + | === Calibrate offset === |
<WRAP center round tip 60%> | <WRAP center round tip 60%> | ||
- | * dbbcif{a,b,c,d,e,f}=2,60 // Set a strong attenuation for each of the IF. | + | * dbbcif{a,b,c,d,e,f}=2,60 //- Set a strong attenuation for each of the IF// |
- | * dbbcif{a,b,c,d,e,f} // Check that each TPI value is in the order between 1000 to 8000. | + | * dbbcif{a,b,c,d,e,f} //- Check that each TPI value is in the order between 1000 to 8000// |
- | * cal_offset={1,2,3,4,5,6} // Launch the cal_offset program for each the Core boards. | + | * cal_offset={1,2,3,4,5,6} //- Launch the cal_offset program for each the Core boards// |
</WRAP> | </WRAP> | ||
+ | |||
+ | One offset calibration per board, so in total it is needed to conduct the offset calibration 6 times. | ||
+ | |||
+ | === Calibrate gain === | ||
+ | |||
+ | <WRAP center round tip 60%> | ||
+ | * dbbcif{a,b,c,d,e,f}=2,agc,1,34000 //- Set an intermediate TPI value (34000) and wait until value reach// | ||
+ | * dbbcif{a,b,c,d,e,f}=2,man //- Set dbbcif with agc off // | ||
+ | * cal_gain={1,2,3,4,5,6} //- Launch the cal_gain program for each the Core boards// | ||
+ | </WRAP> | ||
+ | |||
+ | Again 6 calibrations are needed. | ||
+ | |||
+ | === Calibrate delay === | ||
+ | |||
+ | Do it after the gain and offset calibration. Use similar initial settings for each board as in the Calibration gain procedure. | ||
+ | |||
+ | <WRAP center round tip 60%> | ||
+ | * dbbcif{a,b,c,d,e,f}=2,agc,1,34000 | ||
+ | * dbbcif{a,b,c,d,e,f}=2,man | ||
+ | * cal_delay={1,2,3,4,5,6} //- Launch the cal_delay program for each the Core boards// | ||
+ | </WRAP> | ||
+ | |||
+ | ==== Check calibration's quality ==== | ||
+ | |||
+ | * enablecal=on,on,on | ||
+ | * enableloop | ||
+ | * core3hstats=board_nr | ||
+ | |||
+ | <WRAP center round important 50%> | ||
+ | * All sample powers in a 2% variation | ||
+ | * All bitstats following a proportion of 18-32-32-18% | ||
+ | * Auto-correlation in the order of 2 Million units. | ||
+ | </WRAP> | ||
+ | |||
+ | Last calibration made by Guifré on 19.02.2019. | ||
+ | |||
+ |