AuScope VLBI Operations Wiki hardware

hardware:anemometer

2011-10-26T06:37:12+00:00

Anemometer * [Anemometer interface manual, revision 3] (14-March-20101).

hardware:antenna

2011-10-26T06:37:12+00:00

Antenna Technical Infos: Slew Speeds (deg/s): * Azimuth: 5 * Elevation: 1.25 (approx)

hardware:checklist

2011-10-26T06:37:12+00:00

Feed tube Feed Item Notes Who Status Hobart Yarragadee Katherine Spare LNAs Where they are, get specs, what are Patriot providing? BR, JL N/A Loop couplers Where they are, get specs, what are Patriot providing?

hardware:dbbc.calibration

2013-10-02T03:56:08+00:00

DBBC Calibration * Apply a tone of 764 MHz at -15 dBm to one input 1 of all four CoMos * Use dbbc_config_file_104_calibration.txt * Set dbbcifa/b/c/d=3,agc,1 (i.e. input 3, filter 1) * Once gains have stabilised, turn off the agc loop with dbbc=dbbcgain=all,man

hardware:dbbc.callibration

2014-11-02T23:22:26+00:00

DBBC Calibration * “Phase” calibration Load the default frequency configuration (16 MHz bw, freqs 597, 682, 853 and 938), and connect a tone generator to the inputs of the CoMos. Set up the CoMos to use filter 2 (e.g dbbcifa=1,agc,2). Set the tone to 784

hardware:dbbc.comostatus

2011-10-26T06:37:12+00:00

UTAS label Installed in DBBC… Position Type Notes High filter installed? CM1 Auscope2 A new HL002 A yes CM2 Returned B old Hb B no CM3 Auscope2 C new HL002 C yes CM4 Returned D new HL005 D no CM5 Auscope2 D

hardware:dbbc.currentissues

2012-01-10T21:47:19+00:00

DBBC-HB at Yarragadee * Currently working OK. Occasional jumps in delay now seem to be a Mark5 issue (Jan 2012) * Main problem is low gain through DBBC Conditioning Module B in the upper X-band channel. At the moment we have an alternative firmware config which puts the upper X-band channels through CoMo A and lower through CoMo B. This is giving good results but the underlying problem still needs addressing.

hardware:dbbc.katherine

2018-09-15T05:23:34+00:00

Status after September 2018 visit Read manual, added attenuation to input 10 MHz reduce amplitude to ~-1 dBm rather than 9 dB. Re-tightened internal and external SMA connections - none were loose Removed moderate quantity of bugs from input fan, PSU area.

hardware:dbbc.linux

2012-03-29T02:38:34+00:00

Dave Graham provided a [current version of the Linux implementation on 2010 May 11]. The files were downloaded and placed in a directory on a Linux PC. An empty USB-mounted HDD was used and partitions created to match the first two as described in the READ.ME file provided by Dave. This was done using fdisk

hardware:dbbc.record_config_mk5b

2012-03-29T02:37:07+00:00

Recording Configuration DBBC And Mark5B+ Operator Documentation * First, power cycle the DBBC electronics, via the green switch (marked “EL”) on the rear panel of the DBBC. * Check that the DBBC configuration file (C:\DBBC_CONF\dbbc_config_file.txt) is correct for the experiment you are setting up for. There is no obvious way to change which config file is loaded by DBBC_control so manual editing of this file is necessary. The format is as follows.

hardware:dbbc.reprogram

2016-09-16T16:38:30+00:00

Reprogramming the DBBC Sometimes the DBBC needs reprogramming because channels have been dropped or spectra look strange. To do this, preferable in a gap between scans, follow the following steps: * Open a VNC connection to the DBBC. At Hobart, connect to 131.217.63.248:0

hardware:dbbc.routing

2013-03-28T04:15:55+00:00

Signal path through the DBBC The DBBCs have 4 conditioning modules (CoMos). Each CoMo can take up to 4 input IFs and one of these can be selected to pass through an analogue Nyquist filter. The CoMo also contains an IF amplifier and variable attenuator to get the signal level correct for digitisation.

hardware:dbbc.targetifpower

2018-01-25T03:17:16+00:00

Recommended DBBC IF Power Levels These are the default IF power levels for the three DBBCs. Last updated: 5 May 2014 Telescope ifa ifb ifc ifd Hobart12 40000 48000 32500 35000Hobart26 (fs-mk5hb) 40000 48000 32500 35000Katherine 42000 34000

hardware:dbbc

2012-04-10T02:11:34+00:00

Documentation * Current Issues with the Auscope DBBCs * [Preliminary manual] for using the DBBC under Windows (Dave Graham, 18 April 2010). * DBBC User manual v1.2.3, December 2009 (from Gino) [Word], [PDF] * DBBC Calibration procedure * DBBC back-end wiring configuration * [ DBBC Command Set V2.3] * [A Flexible Environment for VLBI and Space Research: Digital Receiver and Back-end] DBBC Configuration * Conditioning Module Status Supplied 1PPS and 10 MHz reference, using th…

hardware:dbbc.utils_sw

2012-04-05T00:54:45+00:00

3rd Part Utilities and Software The DBBC Control program now has the ability to communicate via a TCP Socket on Port 4000. IVS DBBC Configuration The attached perl code will parse a IVS skd file and program your dbbc for the schedule. Things you will have to modify in the perl script:

hardware:dbbc.windowsxp

2012-08-30T21:10:28+00:00

MS Windows XP Installation I have attached my scanned notes. I used a Univ OEM XP install CD attached to the USB (change the bios to boot of usb cdrom). I loaded the latest drivers for the devices listed, PCI-7200, PCI-9111 & PCIS-DASK V4.29 from

hardware:dbbc3

2019-06-18T00:39:53+00:00

Digital BaseBand Converter 3 Remote Connection Remote connection to dBBC3 can be done via (addr: dbbc3[hb].*): * VNC connection with standard pwd * remote desktop with Windows XP user/pwd === Installation DDC_V_v123 Notes provided in 20.11.2018

hardware:flexbuff

2019-05-22T00:52:11+00:00

Configuring the Flexbuff 2018 Version * Main difference is that the OS system disk is provided by two SSDs attached to the mainboard SATA interface rather than through the RAID card. * To install, boot the flexbuff and after the megaRAID configuration is complete, enter the

hardware:hardware.dbbc.boards

2012-04-05T03:38:02+00:00

Commercial boards used in AuScope & Warkworth DBBC's HSB-835P Rev A 1.0 Motherboard : Network : Intel 82562EZ / 825476I Controller Graphics: Intel 865GV ADLink PCI 7200: ADLink PCI 911HR: It has a FPGA device, documentation says from Xilinx acting as a JTAG interfac…

hardware:hardware.dbbc.install_on_flash_card

2012-03-29T02:43:19+00:00

Installation on a Compact Flash Card Use a fast (133x or better) card with 4 GB or more. We're using a SanDisk Ultra 200x 8 GB. Mounted the CF on a Linux PC via a USB card reader. Card appears as /dev/sde1 As the card is larger than 4 GB I partitioned it to match Dave's card:

hardware:hardware.dbbc.power_measure

2012-04-01T23:31:13+00:00

DBBC Power Measurement New Zealand DBBC 09/06/2011 Testing of DBBC power measurement device reveals that it has a logarithmic output response!! This is for the “dbbcifa” command as it has to cover -3dBm to -48dBm (Gino on site at Warkworth 1/4/2012).

hardware:hardware.dbbc.wiring

2011-10-26T06:37:12+00:00

DBBC Backend wiring configuration This is the wiring as it should be configured at all sites:

hardware:hardware.mark5c

2013-10-02T02:50:59+00:00

We have recently managed use the Mark5C together with DBBC-CD, using the Fila10G and Glapper. The procedure outlined below covers setting up the DBBC & Fila10G, and then making a 1-2 Gbps recording. DBBCConfiguration Start DBBC control program (either DDC v102 or PFB v14) - the configuration files include a line with

hardware:if

2014-07-20T23:20:42+00:00

* RF IF Check

hardware:mark5.conditioning.postconchecks

2014-08-25T01:43:59+00:00

Post Conditioning Checks: Use Dimino and tstdimino to check the vsn and pointer setting after conditioning: dimino -mo -c1 & tstdimino >vsn? >vsn? " need to enter twice to get a nice response" Make sure the vsn is the same as the front label on the module. If it has been corrupted, you can change the vsn by entering:

hardware:mark5.conditioning.times

2012-09-28T00:08:49+00:00

The official list of conditioning times is provided by Haystack in this memo Here is a list of the normal times it takes to condition the various modules: Size (GB) Time (s) Time (hh:mm) 960 2000 4000 22000 6:00 6000 34300 9:30 8000

hardware:mark5.conditioning

2012-09-05T05:22:13+00:00

After disk modules arrive at the stations, they should be conditioned before use. Conditioning performs a read/write cycle over the set of disks and identifies and isolates bad sectors. To Condition a module: Place the module in Bank A (Leave Bank B empty or unlocked)

hardware:mark5.datacheck

2012-02-03T02:00:57+00:00

Following a report from the Washington correlator that the Auscope data was suffering from a large number of dropped frames due to Sync errors (David Hall, 26/1/12 - R4515), we investigated the recorded mark5b data. The results are as follows. Mark5b data format

hardware:mark5.labelnew

2011-10-26T06:37:12+00:00

Get the bar-coded labels, one for the front, one for the back. Get the large square labels (for green/red stickers and temporary labels). Load the module in a recorder. If the bar-coded label says “HOB+0056”, at PCFS prompt: mk5=protect=off mk5=vsn=HOB+0056 mk5=vsn?

hardware:mark5

2012-02-03T00:53:28+00:00

* Setting up a new Mark5B recorder * Disk conditioning * Labeling new disks * Checking mark5b data Mark5B Configuration Installed Debian Etch & mark5b software as per instructions on the haystack website. The pdf & iso's are temporarily located on hobart in ~oper. After this process, the mark5b was ready for use. The only change to the system is that the Mark5B recording server program is no longer invoked by

hardware:phasecal

2019-11-26T00:29:20+00:00

Monitoring Phase Cal tones Recording one scan with Phase Cal ON for 19 minutes using vgos_recorder.py. Followed by another scan of just a couple of minutes with Phase Cal off for comparison. Inifile configured as: Data processing

hardware:rohde_and_schwarz_spectrum_analyser_fsl18

2017-02-08T22:35:54+00:00

Instructions for commands to control the Rohde and Schwarz FSL18 over the ethernet These instructions should work for the 3 GHz spectrum analysers as well, however, they have not been tested and there seem to be some variations as to how different models of the Rohde and Schwarz spectrum analysers interpret these commands (or at least different generations).